It is well documented that when integrated circuits (ICs) are operating they create electronic noise that is disruptive to proper operation if the noise is not controlled. Decoupling capacitors can be used to filter out much of this noise. An example of a typical decoupling capacitor 5 is illustrated in FIG. 1. Silicon substrate 10 forms one of two typical capacitor plates. The substrate is doped with impurities to form a p-type substrate. Thick field oxide 11 is formed to surround areas where the decoupling capacitor is to be placed. A layer of thin oxide 12, also called an insulator layer, is formed to blanket the surface of the entire silicon substrate 10. Next, a layer of conducive material is deposited. Typically used conductive materials are doped polysilicon or a silicide (such as tungsten silicide). These two layers are then patterned and etched to create and define a second decoupling capacitor conductive plate 14 separated from the first plate (substrate 10) by insulator layer 12. Conductive plate 14, oxide layer 12, and the underlying p-type substrate 10 form a typical simple decoupling capacitor. Typically, the decoupling capacitor is covered with a finishing or capping layer 19, which can be made from silicon dioxide.
Decoupling capacitors are designed to maximize the amount of stored charge (or capacitance) per unit area to resist large instantaneous voltage swings. When multiple transistors are switched on and off at any single time, their combined resulting current draw can get very large. This large current draw causes a proportionately large supply voltage drop to the chip. After this drop, it takes time for the supply voltage to reestablish the required supply voltage level needed for regular chip operation. Supply voltage variations can result in logic signal errors and significant physical damage to the chip. To prevent large supply voltage variations, decoupling capacitors are used to store surplus charge on the chip. Therefore, when there is a large draw of current, the surplus charge is used to keep the supply voltage within acceptable limits.
Therefore, one goal for circuit designers is to increase the amount of decoupling capacitance available on a chip. It is known that capacitance is calculated by the equation: C=EA/d; where E is the permitivity of the insulator separating the two capacitor plates 14 and 10; A is the surface area of plate 14 available to store charge; and d is the distance between the two plates 14 and 10. Given the capacitance equation, circuit designers can increase capacitance on a chip by either decreasing the distance between the capacitor plates, or increasing the permitivity and the available area for storing charge. However, the circuit designers have to work within both physical and process limitations when adjusting the capacitance equation variables. Current process techniques have already reached the limits of decreasing the distance between capacitor plates and increasing permitivity thresholds. Therefore, without new processes or materials, the only remaining option for designers is to increase the available area for storing charge.
One standard method to increase capacitance storage area is to increase the size of the particular capacitor plates. This is routinely done by calculating the length times the width of the capacitor's bottom surface area, which is the area available for storing charge. Another standard method, very similar to the first, is to add more capacitors of the same size.
Technological advances, meanwhile, have made it possible to design chips with smaller and more electronic devices, like transistors, to be placed on the same size chip. However, every time more devices are placed on the same size chip, a proportional increase in unwanted electronic noise occurs, requiring a proportional increase in the area needed for placing decoupling capacitors on the chip. As electronic devices are being placed onto the same size chip, a larger area is needed for decoupling capacitors to control the additional noise. These two demands are incompatible given the current state of the technology.
Therefore, circuit designers want a way to design complex circuits without increasing the amount of chip substrate surface area needed for storing more capacitance. Put in another way, circuit designers want a decoupling capacitor design that provides for more capacitance without decreasing circuit design area.
The above described problems with capacitors, and decoupling capacitors in particular, and other problems, are solved through the subject invention and will become more apparent, to one skilled in the art, from the figures, detailed description of the subject invention, and appended claims.